1. Field of the Invention
The present invention relates generally to semiconductor memory devices, particularly to clock-synchronous semiconductor memory devices inputting/outputting data in synchronization with a clock signal, and more particularly to a multi-bank semiconductor memory device having a plurality of banks inside.
2. Description of the Background Art
In recent years, microprocessors (MPUs) has come to have multiple functions, which enables high speed processing of a bulk of data. Accordingly, a Dynamic Random Access Memory (hereinafter referred to as DRAM) for use as main memory, has come to have an increased memory capacity as the miniaturizing techniques have been developed. The operation speed of the DRAM, however, cannot catch up with the operation speed of the MPU and the performance of the entire processing system is degraded with the bottleneck due to the time required for accessing the DRAM and the cycle time of DRAM. In order to prevent the performance of the processing system from being degraded, a high speed memory called cache memory, normally formed of a Static Random Access Memory (SRAM), is installed between a DRAM and an MPU. Data/instruction frequently used by the MPU are stored in the cache memory and such data/instruction are transferred between the MPU and the cache memory. Only when an instruction/data requested for access by the MPU is not present in the cache memory, the DRAM is accessed. It is highly probable that instructions/data required by the MPU are previously stored in the cache memory, and therefore the frequency of accessing the DRAM can be greatly reduced, thereby preventing the operation speed of the processing system from being lowered.
Since the SRAM for use in the cache memory is more expensive than the DRAM, the configuration having such a cache memory installed is not suitable for relatively inexpensive devices such as personal computers. There is therefore a demand for improving the performance of processing system using inexpensive DRAMs. One solution to this is a synchronous DRAM (hereinafter referred to as SDRAM) which is adapted to transfer data in synchronization with a clock signal such as system clock.
In the SDRAM, an operation mode instruction signal is applied in a command form (a combination of the states of a plurality of control signals) in synchronization with a clock signal. In the SRAM, according to this command, a plurality of bits (such as 8 bits per one IO) are selected at a time and these simultaneously selected bits are sequentially output in synchronization with the clock signal. At the time of data writing, data for writing is sequentially taken and written in a prescribed sequence into memory cells simultaneously selected in synchronization with a clock signal.
In the SDRAM, in synchronization with a rising edge of a clock signal, externally applied control signals forming a command, in other words a row address strobe signal /RAS, a column address strobe signal /CAS, a write enable signal /WE, and an address signal and data for writing are taken in for executing internal operation. In synchronization with the clock signal, externally applied data is input and data is output. Therefore it is not necessary to secure a margin for a timing for inputting/outputting data, which takes into consideration of skew (offset in timing) of the control signals and address signals. As a result, the timing for initiating internal operation is rendered faster and therefore the cycle time can be reduced, thus permitting accessing at higher speed.
In a processing system such as image processing system the data bits of serial data addresses are sequentially accessed, while in the processing system a plurality of bits at serial memory positions are frequently accessed because of the localization of the process. Therefore, data is input/output in synchronization with a clock signal, the serial accessing time can be the same as that of the clock signal and the average access time can be comparable to that of the SRAM.
In the SDRAM, the concept of multiple banks is further introduced. More specifically, a plurality of banks are provided in the SDRAM. These banks can be activated and inactivated (precharge) almost independently from each other.
In a standard DRAM, a precharge operation must be performed in order to select a new row. DRAM has its internal signal lines dynamically driven, and therefore each signal line has to be maintained at a prescribed potential level at the time of precharging. For precharging, the time called RAS precharging time tRP is usually necessary (since each internal signal line should be returned to a prescribed potential level.) In the standard DRAM, time called RAS-CAS delay time tRCD is necessary. This is because after a row of memory cells have been selected in response to a row address strobe signal /RAS, a column selecting operation must be executed in response to a column address strobe signal /CAS. Column address strobe signal /CAS must be returned to its inactive state at the of the completion of the column selecting operation. In order to select a memory cell on a new page (a row of memory cells), RAS precharge time tRP and RAS-CAS delay time tRCD are necessary, and therefore the cycle time of a standard DRAM is almost twice its accessing time.
However, if a plurality of banks are provided in the SDRAM, and one bank being activated is accessed while another bank is returned to a precharge state (inactive state), that another bank in the precharge state may be accessed without a waiting time period for RAS precharge time tRP. Therefore, alternately or sequentially activating/precharging (inactivating) these banks permits RAS precharge time tRP to be seemingly eliminated, and therefore high speed accessing is allowed. If one bank is accessed as another bank is precharged and activated, data can be written/read out alternately to/from these banks, time loss by RAS precharge time tRP and RAS-CAS delay time tRCD may be eliminated, and therefore data can be written/read at higher speed.
In the above-described conventional SDRAM, a bank is formed using a memory array (memory mat) as a unit. The memory array (memory mat) has a plurality of memory blocks, and in one memory array, each memory block is driven into a selected or inactive state when a corresponding memory array is activated, and the memory blocks in a memory array cannot be activated/inactivated independently from each other. In the conventional SRAM, the number of banks is as few as the number of memory arrays (memory mats) (usually four banks at most). This is because the array structure of a standard DRAM is employed for the array structure of the SDRAM, row/column decoders are installed separately corresponding to each memory array (memory mat), so that these row/column decoders can be driven independently for each memory array (memory mat).
Use of such a conventional SDRAM with a plurality of banks as a main memory for a processing system will be considered. All the banks of the SDRAM are activated at a time, a row (page) of memory cells are maintained in a selected state in each bank. A sense amplifier provided corresponding to each column of memory cells is used as a pseudo cache. If data/instruction requested by the MPU is not stored in the cache memory (at the time of cache miss), it is determined whether or not the data/instruction requested of accessing by the MPU is present in the selected page of the SDRAM (page hit/miss determination). At the time of page hit, the corresponding page is accessed for transferring the block of data/instructions (cache block) to the cache memory, and the data/instruction requested for acess is transferred to the MPU (for read accessing). Therefore, at page hit, it is requested that the block of the data instructions is selected from the page for reading out, and therefore after elapse of CAS access time ta(CAS) (or CAS latency) the necessary data/instruction may be transferred to cache memory and to the MPU (for read accessing).
Meanwhile, in the case of page miss, the bank storing the data/instruction requested for access is once driven into a precharge state (inactive state), then after the page storing data/instruction required is brought into a selected state, the block including the requested data/instruction is transferred to the cache memory. If the page miss occurs, in the SDRAM, the bank should be once precharged and then activated, and the column must be selected from the selected page. The data/instruction requested is transferred to the cache memory after elapse of the total time period of RAS precharge time tRP, RAS-CAS delay time tRCD, and CAS accessing time ta (CAS) (or CAS latency). During the period, the MPU is in a wait state.
Therefore, if the conventional multi-bank SDRAM is used as a main memory with a small number of banks, the number of pages to be in a selected state is small (the same as the number of banks), its page hit rate is small, and penalty at the time of page miss (the wait time for the MPU) is large.
It is therefore an object of the invention to provide a semiconductor memory device with a new configuration having a plurality of banks with increased page hit rate.
Another object of the present invention is to provide a semiconductor memory device with a plurality of banks capable of accurately inputting/outputting (writing/reading) required data.
Yet another object of the invention is to provide a semiconductor memory device having a plurality of banks, using an array structure similar to a standard DRAM.
A semiconductor memory device according to a first aspect of the invention includes a memory array having a plurality of memory blocks each with a plurality of memory cells arranged in rows and columns, a plurality of local input/output buses provided corresponding to each of these plurality of memory blocks each for transferring data to and from a selected column of a corresponding memory block, a global input/output bus provided in common for the plurality of memory blocks, bank activation circuitry provided corresponding to each of the plurality of memory blocks, selectively activated in response to a first bank address and an operation mode instruction signal for activating a corresponding memory block when activated, a plurality of bank select switches provided between each of the plurality of local input/output buses and the global input/output bus for electrically connecting a corresponding local input/output bus and the global input/output bus when activated, and bank select control circuitry responsive to a column select operation instruction signal and a bank address signal applied simultaneously with the column select operation instruction signal for activating the bank select switch of a local input/output bus provided corresponding to a memory block specified by the simultaneously applied bank address signal.
A semiconductor memory device according to a second aspect includes a memory array having a plurality of memory blocks having a plurality of memory cells arranged in rows and columns and aligned along the direction of columns, a plurality of sense amplifier bands provided between adjacent memory blocks in the memory array for sensing and amplifying data in a memory cell on a column of a corresponding memory block when activated, a plurality of block isolation/connection circuitry provided between each memory block and each of the plurality of sense amplifier bands for connecting each column of a corresponding memory block to a corresponding sense amplifier band when activated, isolation/connection control circuitry for inactivating the block isolation/connection circuitry provided to a memory block sharing a sense amplifier band with a memory block addressed in response to a bank address signal, and sense activation control circuitry provided corresponding to each of the plurality of sense amplifier bands and responsive to the bank address signal and a sense activating signal for activating the sense amplifier band provided to the addressed memory block. The sense activation control circuitry includes a memory for storing bank address data to specify a memory block which has used a corresponding sense amplifier band most recently, and determination circuitry for determining match/mismatch of the bank address data stored in the memory and an applied bank address.
A semiconductor memory device according to a third aspect includes a memory array having a plurality of memory cells arranged in rows and columns, row select circuitry activated in response to array activation instruction signal for selecting a row in the memory array according to a first address signal, reading circuitry activated in response to a read operation instruction signal for selecting the row in the memory array in response to a second address signal simultaneously applied with the read operation instruction signal and reading out the data of memory cells on the selected column externally from the device, and data valid signal output circuitry for outputting externally from the device a data valid signal indicating that the data read out from the reading circuitry is valid in response to the read operation instruction signal.
Since the memory array is divided into a plurality of memory blocks each of which can be driven independently from each other, the number of banks may be increased, and page hit rate may be increased accordingly.
Furthermore, by connecting a local input/output bus and the global input/output bus in response to a signal related to column selection, the local input/output bus and global input/output bus can be connected only at the time of reading/writing operation, thereby permitting a plurality of banks to be activated at a time, and if a sense amplifier is maintained in an active state, the data of a plurality of banks may be prevented from being transferred onto the global input/output bus, and data can be read out accurately using a memory block as a bank.
In the shared sense amplifier configuration in which adjacent memory blocks shares a sense amplifier band, when a bank adjacent to a bank in an active state is accessed, the adjacent memory block in the active state is driven into an inactive state in order to prevent collision of data in the sense amplifier band, and data may be sensed and amplified. Since the inactive state is automatically established inside the device, an external device does not need a mechanism for preventing such collision of data in the sense amplifier band, and therefore the load of control for memory accessing by the external device (memory controller or processor) is alleviated.
In addition, at the time of outputting valid data, the signal indicating that the valid data is output is externally output, and therefore the external device can be accurately notified of the timing for the valid data to be output.
Furthermore, if the confliction is caused for a sense amplifier band, a command input prohibition signal is output externally, the external device can be notified that a countermeasure for preventing such sense amplifier band conflict is executed inside the semiconductor memory device, applying a next mode instruction signal can be surely prevented during the operation period and therefore erroneous accessing to the device may be prevented.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.